1. Field of the Invention
The present disclosure relates to a method of forming a semiconductor device structure and to such a semiconductor device structure. Particularly, the present disclosure relates to processes at the end of front-end-of-line (FEOL) fabrication, particularly at contact formation and silicidation stages.
2. Description of the Related Art
In modern electronic equipment, integrated circuits (ICs) experience a vast applicability in a continuously spreading range of applications. In particular, the demand for increasing mobility of electronic devices at high performance and low energy consumption drives developments to more and more compact devices having features with sizes significantly smaller than 1 μm, the more so as current semiconductor technologies are apt of producing structures with dimensions in the magnitude of 100 nm or less. With ICs representing a set of electronic circuit elements integrated on the semiconductor material, normally silicon, ICs can be made much smaller than any discreet circuit composed of separate independent circuit components. Indeed, the majority of present-day ICs are implemented by using a plurality of circuit elements, such as field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs) or simply MOS transistors, and passive elements, such as resistors, e.g., diffusion resistors, in capacitors, integrated on a semiconductor substrate with a given surface area, wherein typical present-day ICs involve millions of single circuit elements formed on a semiconductor substrate.
The basic function of a FET is that of an electronic switching element, controlling a current through a channel region between two junction regions, referred to as source and drain, by a gate electrode which is disposed over the channel region and to which a voltage relative to source and drain is applied. In common FETs, the channel region extends along the plane between the source and drain regions. Generally, in applying a voltage exceeding a characteristic voltage level to the gate electrode, the conductivity state of the channel is changed and switching between a conducting state or “ON state” and a non-conducting state or “OFF state” may be achieved. It is important to note that the characteristic voltage level at which the conductivity state changes (usually called the “threshold voltage”) therefore characterizes the switching behavior of the FET and it is an issue to keep variations in the threshold voltage level low for implementing a well-defined switching characteristic. However, with the threshold voltage depending nontrivially on the transistor properties, e.g., materials, dimensions, etc., the implementation of a desired threshold voltage value during fabrication processes involves careful adjustment and fine-tuning during the fabrication process, which makes the fabrication of advanced semiconductor devices increasingly complex.
With the sizes of individual FETs having steadily decreased over the last decades, it was observed that strongly-scaled FETs more and more suffered from undesirable effects once the channel length of a FET entered the same order of magnitude as the width of the depletion layer of the source/drain regions. For strongly-scaled FETs, for example, the OFF state leakage current (i.e., the leakage current during the OFF state) increased with the idle power required by the device. Accordingly, these deteriorating effects appearing at small scales and being associated with short channel lengths are frequently referred to as so-called “short channel effects.” In order to continue Moore's Law, tremendous efforts are needed to address the issues of marginalities, variabilities and challenges appearing in the continued scaling towards 20/40 nm VLSI (very large scale integration) MOS technologies such that all the marginalities in each individual process step and all variabilities are properly addressed and, at best, reduced.
With regard to FIGS. 1a and 1b, conventional FEOL processing after silicide formation is shown and described below. FIG. 1a schematically illustrates, in a cross-sectional view, two gate structures 120 and 140 formed on a semiconductor substrate 100, conventionally a silicon substrate. In alignment with the gate structures 120, 140, source/drain regions 112, 114 and 116 are formed within the semiconductor substrate 100. Within the source/drain regions 112, 114 and 116, respective silicide regions 113, 115 and 117 are formed.
The gate structures 120 and 140 comprise respective gate dielectrics 124 and 144, respective gate electrode material layers 126 and 146, e.g., polysilicon material layers, and respective sidewall spacers 128 and 148. The sidewall spacers 128 and 148 cover sidewalls of the respective gate electrode material layers 126 and 146. During a preceding silicidation process, silicide contacts 164 and 168 are formed on the gate electrode material layers 126 and 146.
A distance between two neighboring gate structures, i.e., a distance d1 between the gate structures 120 and 140, continuously decreases with increasing integration density, resulting in issues, such as the formation of voids when filling the space between neighboring gate structures with contact isolation material (which makes the formation of contacts more difficult), with decreasing distance d1 and, accordingly, when less space is available between neighboring gate structures. Generally, the decreasing distance d1 results in less space for implantation and silicidation. A proposal for resolving this situation including a process step for removing spacers after silicide formation is indicated in FIG. 1a by a process step 170. According to conventional techniques, the process step 170 represents a dry etch process that is performed to remove the sidewall spacers 128 and 148 in order to increase the space between neighboring gate structures, i.e., the neighboring gate structures 140 and 120.
With regard to FIG. 1b, the gate structures 120 and 140 are illustrated after the process step 170 is completed. Due to the spacer removal after completion of the process step 170, the distance between the neighboring gate structures 120 and 140 is increased to a distance indicated by d2. In spite of the increased space between the neighboring gate structures 120 and 140, the application of the process 170 results in a loss of active silicon and silicide material, as indicated in FIG. 1b by the broken lines S1, S2 and S3. Herein, each of the broken lines S1, S2 and S3 indicates a surface level of respective source/drain regions 112, 114, 116 and respective silicide regions 113, 115, 117 prior to the application of the process 170. The silicon recess and according silicide loss caused by the process 170 gives rise to several issues, such as a possible ILD pinching during subsequent ILD-related process steps, such as TPEN deposition, and a decrease in a serial resistance due to the caused silicide loss. Therefore, conventional processes in accordance with current VLSI MOS technologies potentially result in devices of significantly degraded device performance.
In view of the above discussion of current VLSI MOS technologies, it is, therefore, desirable to provide a method of forming a semiconductor device structure and such a semiconductor device structure that overcomes the above-described situation.